Decoder implementation using the Shift operators in VHDL

One of the different method of implementing a decoder in VHDL is to use the shift operators of vhdl language. Using these operator can shorten the code and can be extended easily to higher number of input/output bits. Here it is shown how a 3x8 decoder can be implemented using vhdl shift operator and verified and simulated using the active-hdl VHDL software.

Before going to the implementation readers may want to read other ways of implementing decoder. For this follow the following links-

• 74LS138 Decoder design using logical gates
• 74LS138 Decoder design using With Select statement 
• 74LS138 3x8 decoder design with case construct in vhdl
• 74LS138 3x8 decoder design using if else construct

In this vhdl tutorial we gonna see how the shift operator in VHDL can be used to implement a decoder. The idea of using shift operator comes from the fact that there is bit shift in the output of the decoder according the input. If we let x be 4 bit input and y be the 8 bit output then one can observe the output y being in the form- 10000000, 01000000, 00100000, 00010000 ...00000001, which shows that 1 is shifted to the right one bit according to the input x. Now x is 4 bit binary but when it is converted to integer then x as integer indicates the number of shift required.

The following VHDL code illustrates how a decoder could be realized using shift operator in vhdl:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity decoder_shift is
    generic (n : positive := 4);
    port(
    x : in std_logic_vector(n-1 downto 0);
    y : out std_logic_vector(2**n-1 downto 0)
    );
end decoder_shift;

architecture decoder_shift_arch of decoder_shift is
constant yout : bit_vector(2**n-1 downto 0) := (0=>1,others => 0);
begin
    y <= to_stdlogicvector(yout sll to_integer(unsigned(x)));
   
end decoder_shift_arch;


In the above as x input is a std_logic_vector it is first unsigned and then to integer. The shifting operater ssl is used to shift the intermediate signal yout. Since shifting operator ssl acts only on bit_vector, intermediate signal yout is defined as bit_vector. After the shifting the bit_vector is converted back to std_logic_vector using the function to_stdlogic_vector and assigned to the original output y.

The advantage of using shift operator for modelling the decoder is that it requires less code lines to implement the decoder. Another advantage is that it can be easily adopted to higher number of input/output bits by changing the generic bit number n declaration.

The code was simulated with active-hdl vhdl software and the waveform of the simulation is shown below.

Read More..

How to design an ALU in VHDL

Arithmetic Logic Unit is an important part of the CPU or processor. It performs logic operation such as or, and, nand etc and arithmetic functions such as addition, subtraction etc. These operations are performed depending upon the opcode code that is fed into it and produces output depending upon the opcode. Here we show how to design an ALU in VHDL and verify the output. The VHDL code is provided and the design can be simulated in any VHDL Software.

The design of ALU in VHDL is fairly simple. You have to decide what logic and arithmetic operation you wish to the ALU to perform. And you have to give each function an opcode which is some 4 bit code say.

Let x and y be 8 bit input, c be 1 bit carry in to the ALU and z be the output which is also 8 bits.

Then the VHDL code for the ALU is pretty straight forward. The code is below.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu is
    port(x,y: in std_logic_vector(7 downto 0);
    c : in std_logic;
    opcode : in std_logic_vector(3 downto 0);
    z : out std_logic_vector(7 downto 0)   
    );
end alu;

architecture arch of alu is

begin

    with opcode select
   
    -- logic unit
    z <= x when "0000",
    not x when "0001",
    y when "0010",
    not y when "0011",
    x and y when "0100",
    x nand y when "0101",
    x or y when "0110",
    x nor y when "0111",
   
    -- arithmetic unit
   
    x+1 when "1000",
    y+1 when "1001",
    x+y when "1010",
    x-y when "1011",
    0-x+y when "1100",
    0-x-y when "1101",
    x+y-1 when "1110",
    x+y+c when others;
   
end arch;

In the above VHDL code, the when statements was used which is a concurrent statement. Notice that in the code, + and - operators were used in the arithmetic section. Because these operators were used the VHDL library std_logic_unsigned was used. If they were not used then the operator cannot act on the std_logic_vector inputs x and y.

The block diagram and the simulation results are now shown.

Now the simulation results are shown for each of the opcodes.

Logic operation:

Arithmetic operation:

These simulator used was the active hdl vhdl software.

Read More..