Here a CRC generation circuit is build with Xilinx Schematic editor. Below diagram shows the schematic design of CRC generation circuit. It is a 8 bit input and 12 bit output circuit meaning that 4 bits at the end of the 12 bit are the CRC codes appended to the 8 bit data. There are 4 inputs- data(8 bit parallel), Clock, Load and Control. There is one output which is the CRC coded serial output.
Because the ports in the above diagram are not clearly visible it is shown again below-
The 8 bit data enters in parallel into the PISO(Parallel In Parallel Out) block at the lower bottom part of the block diagram. The Load port provides signal to activate the PISO circuit. When it is low that is 0 then the PISO starts performing the conversion. The Clk port provides the clocking function. The Control port controls the overall CRC encoder and is high(logic 1) when the encoding is to be performed.
The PISO outputs serial data from the parallel data. There are 4 flip flops of D type which are all initially set to 0. There are two XOR gate and other combinational circuit gates. The MSB of the PISO enters the the 2nd XOR gate which is XORed with the output of the 4th flip flop(initial 0). The output of this 2nd XOR gate is fed back (1) to the 1st flip flop (2) to the 1st XOR gate both via one AND gate. The output of 1st FF goes to 2nd FF and then to the 3rd FF in each clock cycle. The output of the 3rd FF is XORed with the aforementioned input from the PISO via 2nd XOR plus AND gate. This sequential circuit outputs CRC data then is combined with the data input with the combinational circuit of AND and OR to output the encoded CRC codes.
The PISO(Parallel to Serial Output) was implemented in VHDL and converted to schematic symbol and then added to the schematic page as shown in the above diagram. This was done because the Xilinx schematic editor didnt have a PISO symbol part in its library. One can design any part in VHDL and convert that into schematic symbol for use in schematic editor. This makes Xilinx a great tool for modelling design in the form of block diagram as shown above.
Another blog post which is the sequence detector circuit design with Xilinx Schematic Editor
Because the ports in the above diagram are not clearly visible it is shown again below-
The PISO outputs serial data from the parallel data. There are 4 flip flops of D type which are all initially set to 0. There are two XOR gate and other combinational circuit gates. The MSB of the PISO enters the the 2nd XOR gate which is XORed with the output of the 4th flip flop(initial 0). The output of this 2nd XOR gate is fed back (1) to the 1st flip flop (2) to the 1st XOR gate both via one AND gate. The output of 1st FF goes to 2nd FF and then to the 3rd FF in each clock cycle. The output of the 3rd FF is XORed with the aforementioned input from the PISO via 2nd XOR plus AND gate. This sequential circuit outputs CRC data then is combined with the data input with the combinational circuit of AND and OR to output the encoded CRC codes.
The PISO(Parallel to Serial Output) was implemented in VHDL and converted to schematic symbol and then added to the schematic page as shown in the above diagram. This was done because the Xilinx schematic editor didnt have a PISO symbol part in its library. One can design any part in VHDL and convert that into schematic symbol for use in schematic editor. This makes Xilinx a great tool for modelling design in the form of block diagram as shown above.
Another blog post which is the sequence detector circuit design with Xilinx Schematic Editor
Iron Man.
