Different ways of implementing D Flip Flip with VHDL

Shown below is a table that shows how D flip flop can be implemented in different ways with VHDL. The first row shows the same D flip flop different inputs, that is, with asynchronous and synchronous reset. The second row shows different way of writing the behavior of the D flip flop.

DFF without asynchronous reset	DFF with asynchronous reset	DFF with synchronous enable	DFF with synchronous enable
library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; q : out std_logic; clk : in std_logic ); end dff; architecture dff_arch of dff is begin process(clk) begin if(clkevent and clk = 1)then q <= d; end if; end process; end dff_arch;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; q : out std_logic; rst : in std_logic; clk : in std_logic ); end dff; architecture dff_arch of dff is begin process(clk, rst) begin if(rst = 1)then q <= 0; elsif(clkevent and clk = 1)then q <= d; end if; end process; end dff_arch;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; en : in std_logic; rst : in std_logic; clk : in std_logic; q : out std_logic ); end dff; architecture dff_arch of dff is begin process(clk, rst) begin if(rst = 1)then q <= 0; elsif(clkevent and clk = 1)then if(en = 1) then q <= d; end if; end if; end process; end dff_arch;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; en : in std_logic; rst : in std_logic; clk : in std_logic; q : out std_logic ); end dff; architecture dff_arch of dff is signal int_reg, int_next : std_logic; begin process(clk, rst) begin if(rst = 1)then int_reg <= 0; elsif(clkevent and clk = 1)then int_reg <= int_next; end if; end process; int_next <= d when en = 1 else int_reg; q <= int_reg; end dff_arch;
Implicit function call example	Explicit function call example	No function call, simple edge detect	Using if statement and function call
library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait until rising_edge(clk); q <= d; end process; end dff_behave;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait on clk until rising_edge(clk); q <= d; end process; end dff_behave;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait until clkevent and clk = 1; q <= d; end process; end dff_behave;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait on clk; if rising_edge(clk) then q <= d; end if; end process; end dff_behave;

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