Software Centre: d

This VHDL tutorial shows how D flip flop symbols can be used to implement a block diagram of a shift register and stimulate the design. The shift register has 4 flip flops. So first we need a D flip flop vhdl design then we can use it as component for the top level block diagram.

The VHDL code for the D flip flop is as follows,

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    port(
    clk: in STD_LOGIC;
    rst: in STD_LOGIC;
    D: in STD_LOGIC;
    Q: out STD_LOGIC
    );
    end DFF;

    architecture DFF_arch of DFF is
    begin
process (CLK)
begin
    if CLKevent and CLK=1 then
        if rst=1 then
            Q <= 0;
        else
            Q <= D;
        end if;
    end if;
end process;
    end DFF_arch;

Next we use create the shift register as a block diagram and place the D flip flop symbol that was created earlier into the block diagram. First we need create a new block diagram in the VHDL Software then we need to add its port which are Din, clk and rst as std_logic inputs and Dout which is the std_logic output.

After defining the block diagram we insert four D flip flip into the block diagram and connect them as shown in the following figure.

The VHDL code for the same block diagram is as follows,

library IEEE;
use IEEE.std_logic_1164.all;

entity shift_reg_block is
port(
       Din : in STD_LOGIC;
       clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       Dout : out STD_LOGIC
);
end shift_reg_block;

architecture shift_reg_block of shift_reg_block is

component DFF
port (
       D : in STD_LOGIC;
       clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       Q : out STD_LOGIC
);
end component;

signal Q1, Q2, Q3 : STD_LOGIC;

begin

DFF1 : DFF
port map(
       D => Din,
       Q => Q1,
       clk => clk,
       rst => rst
);

DFF2 : DFF
port map(
       D => Q1,
       Q => Q2,
       clk => clk,
       rst => rst
);

DFF3 : DFF
port map(
       D => Q2,
       Q => Q3,
       clk => clk,
       rst => rst
);

DFF4 : DFF
port map(
       D => Q3,
       Q => Dout,
       clk => clk,
       rst => rst
);

end shift_reg_block;

Now in order to stimulate this design we need to create a testbench. Following is the testbench for this shift register.

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg_block_tb is
end shift_reg_block_tb;

architecture TB_ARCHITECTURE of shift_reg_block_tb is

   component shift_reg_block
   port(
        Din : in STD_LOGIC;
        clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        Dout : out STD_LOGIC );
   end component;

   signal Din : STD_LOGIC;
   signal clk : STD_LOGIC;
   signal rst : STD_LOGIC;

   signal Dout : STD_LOGIC;

begin

   UUT : shift_reg_block
        port map (
            Din => Din,
            clk => clk,
            rst => rst,
            Dout => Dout
        );

   clk_pro : process
   begin
        clk <= 0;
        wait for 5 ns;

        clk <= 1;
        wait for 5 ns;

   end process;

   sti_pro : process
   begin
        Din <= 0;
        wait for 10 ns;

        Din <= 1;
        wait for 10 ns;

        Din <= 1;
        wait for 10 ns;

        Din <= 0;
        wait for 10 ns;

        Din <= 0;
        wait for 10 ns;

        Din <= 1;
        wait for 10 ns;

        Din <= 1;
        wait for 10 ns;

        Din <= 0;
        wait for 10 ns;


   end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_shift_reg_block of shift_reg_block_tb is
   for TB_ARCHITECTURE
        for UUT : shift_reg_block
            use entity work.shift_reg_block(shift_reg_block);
        end for;
   end for;
end TESTBENCH_FOR_shift_reg_block;

The simulation waveform is shown below,

Shown below is a table that shows how D flip flop can be implemented in different ways with VHDL. The first row shows the same D flip flop different inputs, that is, with asynchronous and synchronous reset. The second row shows different way of writing the behavior of the D flip flop.

DFF without asynchronous reset	DFF with asynchronous reset	DFF with synchronous enable	DFF with synchronous enable
library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; q : out std_logic; clk : in std_logic ); end dff; architecture dff_arch of dff is begin process(clk) begin if(clkevent and clk = 1)then q <= d; end if; end process; end dff_arch;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; q : out std_logic; rst : in std_logic; clk : in std_logic ); end dff; architecture dff_arch of dff is begin process(clk, rst) begin if(rst = 1)then q <= 0; elsif(clkevent and clk = 1)then q <= d; end if; end process; end dff_arch;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; en : in std_logic; rst : in std_logic; clk : in std_logic; q : out std_logic ); end dff; architecture dff_arch of dff is begin process(clk, rst) begin if(rst = 1)then q <= 0; elsif(clkevent and clk = 1)then if(en = 1) then q <= d; end if; end if; end process; end dff_arch;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d : in std_logic; en : in std_logic; rst : in std_logic; clk : in std_logic; q : out std_logic ); end dff; architecture dff_arch of dff is signal int_reg, int_next : std_logic; begin process(clk, rst) begin if(rst = 1)then int_reg <= 0; elsif(clkevent and clk = 1)then int_reg <= int_next; end if; end process; int_next <= d when en = 1 else int_reg; q <= int_reg; end dff_arch;
Implicit function call example	Explicit function call example	No function call, simple edge detect	Using if statement and function call
library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait until rising_edge(clk); q <= d; end process; end dff_behave;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait on clk until rising_edge(clk); q <= d; end process; end dff_behave;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait until clkevent and clk = 1; q <= d; end process; end dff_behave;	library ieee; use ieee.std_logic_1164.all; entity dff is port( d, clk : in std_logic; q : out std_logic ); end dff; architecture dff_behave of dff is begin process begin wait on clk; if rising_edge(clk) then q <= d; end if; end process; end dff_behave;

Software Centre

VHDL tutorial on Shift Register Design using D Flip Flop as component

Different ways of implementing D Flip Flip with VHDL

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