VHDL Programming tutorial on Priority encoder

Priority Encoder is an important class of Encoder. It is different from a ordinary encoder in that it gives priority to the input signal. The signal corresponding to the higher priority is outputted by the Priority encoder.

Here the design of 8 to 3 priority encoder is taken as an example for VHDL programming tutorial.

The truth table of a 8 to 3priority encoder is shown below:

In the truth table, the input data is x7x6x5x4x3x2x1x0 which is 8 bit input. And the 3 bit output is y2y1y0. The z signal indicates a condition that all input bits are 0 which is also a possible combination.

The priority is the signal with input 1XXXXXXX where X indicates dont care which means it does not matter whether it is 0 or 1. The next priority goes to 01XXXXXX and so on up on the table.

Suppose if 10100110 is the input data then the output is 111.

Below is the VHDL code for this 8 to 3 priority encoder:

library ieee;
use ieee.std_logic_1164.all;

entity prio_encoder is
    port(
    x : in std_logic_vector(7 downto 0);
    y : out std_logic_vector(2 downto 0);
    z : out std_logic
    );
end prio_encoder;

architecture model of prio_encoder is
begin
   
    process(x)
    begin
        if (x(7) = 1) then y <= "111";
        elsif (x(6) = 1) then y <= "110";
        elsif (x(5) = 1) then y <= "101";
        elsif (x(4) = 1) then y <= "100";
        elsif (x(3) = 1) then y <= "011";
        elsif (x(2) = 1) then y <= "010";
        elsif (x(1) = 1) then y <= "001";
        else y <= "000";
        end if;
       
        end process;
       
        z <= 0 when x = "00000000" else 1;           

end model;

In the above code, we used if elsif then statement of VHDL to implement the priority encoder. Since the if statement is a sequential state it is written inside the Process statement with sensitivity signal as x. The first statement is checked first and then next statement inside a process since the statements are sequential. If the first statement is true then the output is send to the output and the process exits. If not then the second statement is checked and if it evaluates true then it corresponding output is outputted and so on. So this code implements priority.The last else statement is needed so that the synthesizer does not create a latch. That is all combination of the input must be included. Finally the z output when all inputs are 0s is implemented outside the process statement.

The simulated waveform is shown below:

Encoders are important part of a digital system. There are other application of encoders such as code conversion encoders and includes designs that needs to be encoded to reduce output signals.

Read More..

VHDL tutorial on Shift Register Design using D Flip Flop as component

This VHDL tutorial shows how D flip flop symbols can be used to implement a block diagram of a shift register and stimulate the design. The shift register has 4 flip flops. So first we need a D flip flop vhdl design then we can use it as component for the top level block diagram.

The VHDL code for the D flip flop is as follows,

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    port(
    clk: in STD_LOGIC;
    rst: in STD_LOGIC;
    D: in STD_LOGIC;
    Q: out STD_LOGIC
    );
    end DFF;

    architecture DFF_arch of DFF is
    begin
process (CLK)
begin
    if CLKevent and CLK=1 then 
        if rst=1 then   
            Q <= 0;
        else
            Q <= D;
        end if;
    end if;
end process;
    end DFF_arch;

Next we use create the shift register as a block diagram and place the D flip flop symbol that was created earlier into the block diagram. First we need create a new block diagram in the VHDL Software then we need to add its port which are Din, clk and rst as std_logic inputs and Dout which is the std_logic output.

After defining the block diagram we insert four D flip flip into the block diagram and connect them as shown in the following figure.

The VHDL code for the same block diagram is as follows,

library IEEE;
use IEEE.std_logic_1164.all;

entity shift_reg_block is
  port(
       Din : in STD_LOGIC;
       clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       Dout : out STD_LOGIC
  );
end shift_reg_block;

architecture shift_reg_block of shift_reg_block is

component DFF
  port (
       D : in STD_LOGIC;
       clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       Q : out STD_LOGIC
  );
end component;


signal Q1, Q2, Q3 : STD_LOGIC;

begin

DFF1 : DFF
  port map(
       D => Din,
       Q => Q1,
       clk => clk,
       rst => rst
  );

DFF2 : DFF
  port map(
       D => Q1,
       Q => Q2,
       clk => clk,
       rst => rst
  );

DFF3 : DFF
  port map(
       D => Q2,
       Q => Q3,
       clk => clk,
       rst => rst
  );

DFF4 : DFF
  port map(
       D => Q3,
       Q => Dout,
       clk => clk,
       rst => rst
  );

end shift_reg_block;

Now in order to stimulate this design we need to create a testbench. Following is the testbench for this shift register.

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg_block_tb is
end shift_reg_block_tb;

architecture TB_ARCHITECTURE of shift_reg_block_tb is

    component shift_reg_block
    port(
        Din : in STD_LOGIC;
        clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        Dout : out STD_LOGIC );
    end component;

    signal Din : STD_LOGIC;
    signal clk : STD_LOGIC;
    signal rst : STD_LOGIC;

    signal Dout : STD_LOGIC;

begin

    UUT : shift_reg_block
        port map (
            Din => Din,
            clk => clk,
            rst => rst,
            Dout => Dout
        );

    clk_pro : process
    begin
        clk <= 0;
        wait for 5 ns;
       
        clk <= 1;
        wait for 5 ns;
       
    end process;
  
    sti_pro : process
    begin
        Din <= 0;
        wait for 10 ns;
       
        Din <= 1;
        wait for 10 ns;
       
        Din <= 1;
        wait for 10 ns;
       
        Din <= 0;
        wait for 10 ns;
       
        Din <= 0;
        wait for 10 ns;
       
        Din <= 1;
        wait for 10 ns;
       
        Din <= 1;  
        wait for 10 ns;
       
        Din <= 0;
        wait for 10 ns;

       
    end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_shift_reg_block of shift_reg_block_tb is
    for TB_ARCHITECTURE
        for UUT : shift_reg_block
            use entity work.shift_reg_block(shift_reg_block);
        end for;
    end for;
end TESTBENCH_FOR_shift_reg_block;

The simulation waveform is shown below,

Read More..