Op Amp design tutorial using IC741

Operational amplifier finds many application in electronics design. They are one of the corner stone building blocks of any electronics system. They were conceived in early 1940s but were made available in 1952 using vaccum tubes. In this op amp design tutorial, operational amplifier circuit analysis in various application setting are described with illustration using the IC741.

Operational amplifier applications includes circuit design that requires mathematical functions such as adder, subtractor, multiplier, divider, integrator and differentiators. Not only can they be used to realize mathematical function but also realize inverting, non-inverting amplifier, unity gain amplifier(buffer) and also op-amp comparator.

Inverting Operational Amplifier Circuit Analysis

The inverting operational amplifier circuit is shown below. The circuit uses IC741 op-amp. An ac signal is applied at the inverting input and the non-inverting input is grounded. A dc signal can also be applied to the inverting input instead of ac signal. The R1 and RF resistors are the input and the feedback resistors respectively.

One can derive an equation that relates the input and output voltages using two KVL equations. The input and the output voltage relation is,

vout = - vin*(Rf/R1)

 To derive the input and output voltage relation for the inverting operational amplifier it is helpful to remember two things- Consider that the op-amp is ideal then in absence of any input source there is no current flowing either into the two input terminals and that there is no voltage difference between the two input terminals.

Then after ac source(or dc source) is applied to the inverting terminal of the op-amp, the current i flows into R1 then goes into Rf and appears at the output. In this case we can apply KVL as follows,
[v_{in}=iR_1+iR_f+v_{out}]
or,
[v_{out}=v_{in}-i(R_1+R_f)]
Then we derive another KVL equation using the fact that since there is no voltage difference between the two terminal then the voltage at the point X as shown in the figure below is also at Zero volt because the non-inverting terminal is at Zero volt.

The point X is also called virtual ground. The KVL equation considering this gives us-
[v_{in}=iR_1]
Substituting i from this equation into the above equation we get the relation between the input an output voltage for the inverting amplifier as follows,
[v_{out}=-v_{in}(frac{R_{f}}{R_{1}})]
 The ratio Rf/R1 is called the gain or attenuation of the inverting op-amp. If Rf is greater than R1 then we have an amplifier and if Rf is less than R1 then we have an attenuator. The negative sign in the equation shows that the output voltage signal is out of phase with the input voltage signal.

The following graph shows the input and the output voltages waveforms;


The input voltage is 1V ac signal and the output voltage is amplified 2V ac signal. Notice that they are out of phase by 180 degree which is due to the negative sign in the output voltage equation above.

Non-Inverting Operational Amplifier Circuit Analysis

Next consider the circuit design of a non-inverting op-amp. In this case the input is applied to the non-inverting input terminal of the op-amp. The inverting terminal is grounded via a resistor(R1). The feedback from the output terminal is taken to the input terminal at the inverting terminal. This circuit is shown below,

In this case the output voltage is,
[v_{out}=v_{in}(1+frac{R_{f}}{R_{1}})][v_{out}=v_{in}(1+frac{R_{f}}{R_{1}})]
The absence of the negative sign indicates that the output voltage is in phase with the input voltage.

The following graph shows the output voltage and the input voltage waveform.

The above waveform graph illustrates that the input and output voltages are in phase and that the output voltage is amplified.

Adder Operational Amplifier Circuit Analysis

Op-amps can be used for doing mathematical operation. One is the addition of analog continuous signal. The adder operational amplifier circuit is shown below.

In the adder circuit above, the input V1, V2 and V3 have amplitude of 1V, 2V and 3V respectively and all had the same frequency of 10Hz. These input were connected together and applied at the inverting input of the IC741. The resistor values are the same so that the output voltage is the sum of the 3 inputs, that is the output signal has 6V(1V+2V+3V). Had we taken different value of Rf(i.e the feedback resistor) but same input resistor values then we would have amplified the signal and not 6V. In the circuit above we took 10K ohm resistor but we could have equally taken 1K ohm resistor for all of those resistors or any other value of resistance.

The output voltage in terms of input voltage and resistor values is,
 [v_{out}=-(v_{1}+v_{2}+v_{3})(frac{R_{f}}{R})]
 Now the following shows the waveform of various inputs and output.

The 3 input voltages with frequency of 10Hz.

The following shows the Vin at the input terminal of the op-amp.

Then the following is the output voltage waveform which has 6V amplitude,

Difference/Differential Operational Amplifier Circuit Analysis

 Another application of the op-amp is realizing a subtractor or a difference or differential amplifier. Here two signal which are to be subtracted are applied at the non-inverting and inverting terminals of the op-amp. The op-amp outputs the difference signal given that the input resistors at the input terminals and the feedback resistor are the same.

The differential operational amplifier circuit is shown below,

 In the above differential op amp circuit design, the input V1 has amplitude of 1V and the input V2 has amplitude of 3V and both have frequency of 10Hz. The output should be an ac signal with amplitude 2V(3V-1V).

The equation relating the output and inputs signal for the difference amplifier is,
[v_{out}=v_{2}-v_{1}]



Voltage Follower/ Unity Gain Amplifier/ Buffer Operational Amplifier Circuit Analysis

 Another application of operational amplifier is buffering signal. Why this is essentially useful is that it signal which are distorted can be smoothed using buffer and also the input signal can be delayed or saved or buffered for certain time. Such circuit is also called voltage follower because the output signal is the same as the input signal, that is same in respect to magnitude and phase. The circuit is also called unity gain amplifier because the output signal is not amplified, in other words, the magnitude of the output signal is not increased.

The following figure shows the voltage follower operational amplifier circuit,

 The mathematical relation between the output and input signal is very simple:
Vout=Vin

The following waveform graph shows the output and input signal waveform which are overlapping.

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VHDL Programming tutorial on Priority encoder

Priority Encoder is an important class of Encoder. It is different from a ordinary encoder in that it gives priority to the input signal. The signal corresponding to the higher priority is outputted by the Priority encoder.

Here the design of 8 to 3 priority encoder is taken as an example for VHDL programming tutorial.

The truth table of a 8 to 3priority encoder is shown below:

In the truth table, the input data is x7x6x5x4x3x2x1x0 which is 8 bit input. And the 3 bit output is y2y1y0. The z signal indicates a condition that all input bits are 0 which is also a possible combination.

The priority is the signal with input 1XXXXXXX where X indicates dont care which means it does not matter whether it is 0 or 1. The next priority goes to 01XXXXXX and so on up on the table.

Suppose if 10100110 is the input data then the output is 111.

Below is the VHDL code for this 8 to 3 priority encoder:

library ieee;
use ieee.std_logic_1164.all;

entity prio_encoder is
    port(
    x : in std_logic_vector(7 downto 0);
    y : out std_logic_vector(2 downto 0);
    z : out std_logic
    );
end prio_encoder;

architecture model of prio_encoder is
begin
   
    process(x)
    begin
        if (x(7) = 1) then y <= "111";
        elsif (x(6) = 1) then y <= "110";
        elsif (x(5) = 1) then y <= "101";
        elsif (x(4) = 1) then y <= "100";
        elsif (x(3) = 1) then y <= "011";
        elsif (x(2) = 1) then y <= "010";
        elsif (x(1) = 1) then y <= "001";
        else y <= "000";
        end if;
       
        end process;
       
        z <= 0 when x = "00000000" else 1;           

end model;

In the above code, we used if elsif then statement of VHDL to implement the priority encoder. Since the if statement is a sequential state it is written inside the Process statement with sensitivity signal as x. The first statement is checked first and then next statement inside a process since the statements are sequential. If the first statement is true then the output is send to the output and the process exits. If not then the second statement is checked and if it evaluates true then it corresponding output is outputted and so on. So this code implements priority.The last else statement is needed so that the synthesizer does not create a latch. That is all combination of the input must be included. Finally the z output when all inputs are 0s is implemented outside the process statement.

The simulated waveform is shown below:

Encoders are important part of a digital system. There are other application of encoders such as code conversion encoders and includes designs that needs to be encoded to reduce output signals.

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VHDL tutorial on Shift Register Design using D Flip Flop as component

This VHDL tutorial shows how D flip flop symbols can be used to implement a block diagram of a shift register and stimulate the design. The shift register has 4 flip flops. So first we need a D flip flop vhdl design then we can use it as component for the top level block diagram.

The VHDL code for the D flip flop is as follows,

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    port(
    clk: in STD_LOGIC;
    rst: in STD_LOGIC;
    D: in STD_LOGIC;
    Q: out STD_LOGIC
    );
    end DFF;

    architecture DFF_arch of DFF is
    begin
process (CLK)
begin
    if CLKevent and CLK=1 then 
        if rst=1 then   
            Q <= 0;
        else
            Q <= D;
        end if;
    end if;
end process;
    end DFF_arch;

Next we use create the shift register as a block diagram and place the D flip flop symbol that was created earlier into the block diagram. First we need create a new block diagram in the VHDL Software then we need to add its port which are Din, clk and rst as std_logic inputs and Dout which is the std_logic output.

After defining the block diagram we insert four D flip flip into the block diagram and connect them as shown in the following figure.

The VHDL code for the same block diagram is as follows,

library IEEE;
use IEEE.std_logic_1164.all;

entity shift_reg_block is
  port(
       Din : in STD_LOGIC;
       clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       Dout : out STD_LOGIC
  );
end shift_reg_block;

architecture shift_reg_block of shift_reg_block is

component DFF
  port (
       D : in STD_LOGIC;
       clk : in STD_LOGIC;
       rst : in STD_LOGIC;
       Q : out STD_LOGIC
  );
end component;


signal Q1, Q2, Q3 : STD_LOGIC;

begin

DFF1 : DFF
  port map(
       D => Din,
       Q => Q1,
       clk => clk,
       rst => rst
  );

DFF2 : DFF
  port map(
       D => Q1,
       Q => Q2,
       clk => clk,
       rst => rst
  );

DFF3 : DFF
  port map(
       D => Q2,
       Q => Q3,
       clk => clk,
       rst => rst
  );

DFF4 : DFF
  port map(
       D => Q3,
       Q => Dout,
       clk => clk,
       rst => rst
  );

end shift_reg_block;

Now in order to stimulate this design we need to create a testbench. Following is the testbench for this shift register.

library ieee;
use ieee.std_logic_1164.all;

entity shift_reg_block_tb is
end shift_reg_block_tb;

architecture TB_ARCHITECTURE of shift_reg_block_tb is

    component shift_reg_block
    port(
        Din : in STD_LOGIC;
        clk : in STD_LOGIC;
        rst : in STD_LOGIC;
        Dout : out STD_LOGIC );
    end component;

    signal Din : STD_LOGIC;
    signal clk : STD_LOGIC;
    signal rst : STD_LOGIC;

    signal Dout : STD_LOGIC;

begin

    UUT : shift_reg_block
        port map (
            Din => Din,
            clk => clk,
            rst => rst,
            Dout => Dout
        );

    clk_pro : process
    begin
        clk <= 0;
        wait for 5 ns;
       
        clk <= 1;
        wait for 5 ns;
       
    end process;
  
    sti_pro : process
    begin
        Din <= 0;
        wait for 10 ns;
       
        Din <= 1;
        wait for 10 ns;
       
        Din <= 1;
        wait for 10 ns;
       
        Din <= 0;
        wait for 10 ns;
       
        Din <= 0;
        wait for 10 ns;
       
        Din <= 1;
        wait for 10 ns;
       
        Din <= 1;  
        wait for 10 ns;
       
        Din <= 0;
        wait for 10 ns;

       
    end process;

end TB_ARCHITECTURE;

configuration TESTBENCH_FOR_shift_reg_block of shift_reg_block_tb is
    for TB_ARCHITECTURE
        for UUT : shift_reg_block
            use entity work.shift_reg_block(shift_reg_block);
        end for;
    end for;
end TESTBENCH_FOR_shift_reg_block;

The simulation waveform is shown below,

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